Tips for Testing Panelized Boards at ICT

Don't forget to download the Excel spreadsheet that goes with this technical note.

We often see cases where boards are built in a Panel, where the automatic placement machines are loading several boards at once. It is sometimes convenient to test them when they are panelized since it removes the cost burden in labor for the handling time. Some boards are panelized with as few as two boards on a panel (which is termed "2-up"), and I have seen as many as sixty-three to a panel ("63-up"). There are several guidelines which need to be considered when testing panelized boards, which include:

  • Most In-Circuit Testers have a tool for copying the test from the first board on a panel to the other boards. For example, for a 3-up panel, you would debug the first board, then execute some "Multipanel Software" that will create the programs for boards 2 and 3. You would usually use an easy number to offset the boards, like nodes 1-199 for Board 1, 201-399 for Board 2, and 401-599 for Board 3.

  • Realize that your yield will be lower. If you are running a 10-up panel, and if the individual board has a yield of 97%, then your yield for the panel will be 0.9710, which is only 73.75%. Therefore, instead of 3% of your boards being kept for repair, 24% are kept as panels in the repair loop!

  • Boards tend to break out of their panels, so it is important to ensure your fixture can test an individual board. A good means of doing this is to have your fixturing vendor make a special well for the individual board, and wire it in parallel with the first board in the panel. The first test program can then be executed if a single board test is needed. Another means of achieving this is to have a plexiglass cover over all boards except the first well, and simply execute the program for the first board.

  • Realize that the raw card vendors will have manufacturing defects, and these boards will usually have an X drawn over the board. The automatic insertion machines will pick up this X with optics telling the machine not to load parts on that board. A term that is used for this is an "X-Out". The Test Engineer needs to be aware of X-Out possibilities by providing a means of skipping a test if a board is not loaded. Two means exist for solving this:

    1. Let the Operator enter the board number(s) that have X-Outs, and fix the test program to skip these tests. A test should be added to ensure the Operator³s response is correct. Automatically test to see if parts are loaded by using Ignore Failure, and testing a few parts to determine if they are present. If several devices are not present, report an X-Out; if at least one is present, continue the test.

    2. Automatically test to see if parts are loaded by using Ignore Failure, and testing a few parts to determine if they are present. If several devices are not present, report an X-Out; if at least one is present, continue the test.

  • If a board fails the test, it is wise to re-test the entire panel. The basic reasoning is that the board has been touched with a soldering iron, and perhaps more than the failing board was modified!

  • Some Users have found it awkward to use a different directory for each board, so be aware that these can be merged into one program. This has another advantage of a faster test time if all devices are tested together. For example, on a 16-up panel, if all the R1 devices are tested together, then the autoranging hardware is set for all 16 tests, and the test will be faster. It is cumbersome to generate a program this way because somehow you have to distinguish the board number being tested. Some Users will use a nomenclature in the ID field like "R1 (1)" for R1 on the first panel; other Users will have the board number under the Name or the Description. It would also be necessary to handle X-Out Boards with the Flow Control for every test. This is a myriad of work, but can be useful in high-volume applications to simplify changes and to reduce test time.

  • Power wiring can be difficult for panelized boards. It is obvious that power should not be wired in parallel for each board, or all the Power Capacitors will be in parallel. I would usually wire power through User Relays in the tester (when available).

  • Care should be taken to easily identify the failing board(s).

  • During the design cycle make sure the individual boards have tooling holes. It is difficult to test individual boards for retest when the tooling holes are on the panelized board³s break-away! If the first well is used to test individual boards, then the tooling pins can be placed on the first board³s pins and on the other standard places.

  • Since testing occurs before the boards are broken away from the panels, it is important to ensure that the depanelization process does not cause defects. Many panels are broken into individual boards by bending the panel until they snap apart; the can cause opens for SMT boards. Using a tool to hold the board in place or using perforated edges can preclude failures after ICT.

  • Remember that virtually the only reason to test in a panel is to reduce the handling time of the board. You will always have handling time on panelized boards unless you use dual chamber fixtures. Therefore, consider the dual chamber fixture instead of testing boards in a panel as a default. The extra fixturing and programming cost do not always pay for themselves!!

  • Lastly, be aware that panelized boards will take a larger number of tester pins, so be sure that the number of nodes on each board times the number of board on the panel are less than the tester pins available. Notice also that is very convenient to allow the offsets to be in even numbers, so a four-up panel could have the first board starting at Node 0, the second at Node 200, the third at Node 400, and the fourth at node 600 (remembering you will need a tester with about 800 Nodes for this).

In order to assist in making sure that the extra Non-Recurring Engineering costs (for the fixture and the program) to test boards in a panel will pay for itself, I have provided a Excel-compatible file called PANEL.XLS. This spreadsheet will allow you to enter the general information on the board (such as the volume of boards, the number of boards in a panel, the estimated test time, etc.), and it will calculate for you the volume of boards and the number of years that it will take to recover the initial costs. This is provided at no charge, and also includes similar calculations for justifying dual chamber fixtures. Please be aware that this spreadsheet does not take all variables into consideration (such as extra repair, parts and test costs for cases where the repair technician replaces a component on the wrong board of the panel). The intention is to provide an estimate of the Return-On-Investment for testing boards in a panel, and the errors in the estimated volumes and test times will always keep such calculations inaccurate.

Prepared By:

Vaughan Carlson
President
VALUE Engrafting
(256) 426-8808
Vaughanc@valueeng.com